1. Field of the Invention
The invention relates in general to a buck converter, and more particularly to a multi-phase buck converter.
2. Description of the Related Art
The buck converter is a practical converter for providing an output voltage smaller than the input voltage so as to step down the voltage. Referring to FIG. 1, a conventional buck converter is shown. The buck converter 100 comprises an NMOS switch M11, an NMOS switch M12, an inductance L11 and a capacitor C11. The buck converter 100, according to an input voltage Vin1, outputs an output voltage Vout1 smaller than the voltage value of the input voltage Vin1. The drain of the NMOS switch M11 receives the input voltage Vin1, and the gate of the NMOS switch M11 receives a control signal S11. The drain of the NMOS switch M12 is coupled to the source of the NMOS switch M11, the gate of the NMOS switch M12 receives a control signal S12, and the source of the NMOS switch M12 is connected to the ground. The NMOS switch M11 and the NMOS switch M12 respectively receive the control signal S11 and control signal S12 to determine whether to be turned on. When the NMOS switch M11 is turned on, the NMOS switch M12 is turned off. When the NMOS switch M12 is turned on, the NMOS switch M11 is turned off.
Under the configuration of the buck converter 100, Vout1/Vin1=D, wherein D denotes a duty cycle. During a period T, the length during which the NMOS switch M11 is turned on is equal to DT, then the length during which the NMOS switch M12 is turned on is equal to (1−D)T. That is, during a period, the value of the output voltage is controlled by adjusting the length during which the switch element is turned on.
To avoid a switch element being overloaded and resulting in concentration of heat when providing an output voltage, multi-phase converting is used to facilitate the dissipation of the heat. Referring to FIG. 2, a conventional multi-phase buck converter is shown. The multi-phase buck converter 200, according to an input voltage Vin2, outputs a voltage smaller than an output voltage Vout2. The multi-phase buck converter 200 comprises six NMOS switches M21˜M26 and three inductances L21˜L23 and a capacitor C21. The NMOS switches M21 and M22 are controlled by the control signals S21 and S22, and generate a current I21 by the inductance L21. The NMOS switches M23 and M24 are controlled by control signals S23 and S24, and generate a current I22 by the inductance L22. The NMOS switches M25 and M26 are controlled by control signals S25 and S26, and generate a current I23 by the inductance L23.
Suppose the average current I24 is 120 A, each phase receives 40 A, that is, the average of the sum of the currents I21, I22 and I23, hence avoiding the heat being overcentralized. Referring to FIG. 3, a relevant signal wave pattern of the conventional multi-phase buck converter is shown. The phase of the control signal S21 is inverse to the phase of the control signal S22, the phase of the control signal S23 is inverse to the phase of the control signal S24, and the phase of the control signal S25 is inverse to the phase of the control signal S26. The current I21 fluctuates along with the control signal S21, the current I22 fluctuates along with the control signal S23, and the current I23 fluctuates along with the control signal S25. The currents I21, I22 and I23 are merged to form the current I24 fluctuating around the average value 120 A as shown in FIG. 3.
When the number of phases increases, the power storing frequency Fsw of the inductance increases accordingly, causing the peak current of the current to decrease relatively according to the formula: I2R=P, so that both the conduction loss and the switching power loss decrease accordingly. When the power storing frequency Fsw increases, the frequency width is increased, and the capacitor does not need to store too much power. Thus, the value or the number of capacitors may be reduced to reduce the costs.
However, if the power storing frequency Fsw is increased by directly increasing the switching frequency of the switch, power loss also increases accordingly. In addition, by adding an additional phase to increase the power storing frequency Fsw, corresponding elements such as switch element, inductance and output signal controller also need to be incorporated, hence extra costs are incurred. Therefore, how to increase the power storing frequency Fsw and at the same time avoid the abovementioned disadvantages has become an imminent issue to be resolved.